ARTICLE NOVEMBER 2002

PIVOTAL ROLE FOR ELECTRONIC DESIGN AUTOMATION

Design automation is playing an increasingly pivotal role in the electronics industry as the era of the complete system-on-a-chip (SoC) dawns. Very deep submicron technologies make it possible to provide chips with more than 100 million gates and with clock frequencies well over 1 GHz. However, SoC devices pose major interconnection and verification problems - requiring particular attention to design for manufacturing (DFM) and design for testing (DFT).

Current 0.18-?m silicon technology enables up to 5.10⁶ gates/cm² and is capable of handling up to 1000 million instructions a second (MIPS) per Watt with clock frequencies up to 720 MHz. By 2004, 90 nm technology should make possible 30.10⁶ gates/cm², handling up to 2200 MIPS/W and clock frequencies up to 1300 MHz. And by 2011, 50 nm technology will make it possible to have 200.10⁶ gates/cm², handling 4000 MIPS/W and clock frequencies up to 2 GHz.

Applications for these new circuits will include sophisticated automotive control systems for safer and more-energy-efficient cars, high-performance yet easy-to-use consumer electronics and versatile, yet secure, mobile Internet multimedia terminals offering a much higher quality of service with a choice of connectivity (VDSL, wireless, optical?) and able to handle services such as video on demand. These devices will offer a high level of functional intelligence - improving man-machine interfaces, automating translations and simplifying communications.

Electronic design automation is essential to make the best of these new technologies. Software is now responsible for 80% of system development costs, verification takes two to three times more development effort than the design itself, and non-recurring engineering (NRE) costs at the design stage can be more than ten times higher than NRE in manufacturing. And design turnaround time can be measured in months or years when manufacturing turnaround is measured in weeks. More importantly, without much improved design for testing, test costs per gate grow exponentially relative to manufacturing cost.

Yet EDA is an area where there has been a major gap in Europe - and the specialised nature of many European applications makes them unattractive for support by the major global - mainly US-based - EDA manufacturers. MEDEA+ therefore identified a need to improve EDA from the beginning of its operations.

There are already six MEDEA+ projects involved in the EDA area - ranging from the system level and architectural exploration in the A502 Multi-processor embedded systems architectures (MESA) project to design for testability, debugging and efficiency in the A503 Advanced solutions for SoC innovative testing in Europe (ASSOCIATE) project.

MESA (A502)

MESA is developing flexible platforms for multi-processor architecture design covering a broad spread of applications that harness the powerful computational capabilities of 100-nm technology. Efficient design methods are essential for reconfigurable multi-processor architectures to simplify analysis of the application domains, define communications protocols, and validate the resulting solutions.

Digital cell phones are the single largest user of such components with almost 400 million handsets manufactured each year and an average annual growth of around 65%. Europe currently enjoys a strong position in this technology, as well as in the consumer and data processing sectors, where integrated system design is equally important. By eliminating a serious bottleneck, MESA will do much to help maintain this lead in both application-specific integrated circuit (ASIC) devices designed for a specific customer, and application-specific standard products (ASSPs), which meet the needs of multiple users.

ANASTASIA+ (A510)

Analogue and mixed analogue-digital signal (A/MS) circuits and systems are used for an ever-growing variety of functions in automotive electronics, data communications and wireless telecommunications. Europe has a lead in application-specific A/MS chips, but needs to improve design automation to meet increasingly sophisticated market demands. The MEDEA+ A510 Analogue enhancements for a system-to-silicon automated design (ANASTASIA+) project is developing new tools for a top-down approach in mixed signal environments. The goal is significant improvements in A/MS design automation, covering the complete system environment, with a high level of automation and reuse.

SpeAC (A508)

Appropriate system design architecture is crucial for efficient implementation of complex algorithms found in advanced electronic applications. Raising the level of abstraction at which creative work is performed is the most effective means of improving design efficiency, particularly for SoCs in mixed signal environments. The MEDEA+ A508 SpeAC project is targeting the level above hardware/software co-design with two platform-based approaches - architecture-algorithm co-design, and component-based design for heterogeneous systems - for highly complex applications in the automotive and communications areas. The goal of the project is the development of EDA tools that are much better tuned to the needs of European industry than those from US EDA manufacturers.

Genuine intellectual property (IP) verification and reuse is another key area selected by MEDEA+. While such reuse offers a good solution in theory - a 90% reuse would speed up design by a factor of ten - it does not always work in practice. Savings in design time are often lost in increased verification costs as the elements concerned have frequently been developed and tested under different conditions.

The answer could come from high-level language (HLL) descriptions as a system level design language would provide a reproducible vehicle of exchange. Europe is already leading the USA in the use of 'System C' - based on C++ class libraries - as an open source standard language for system-level design and IP modelling, and XML could provide a new 'envelope' approach that would make IP exchange more credible.

TOOLIP (A511)

The MEDEA+ A511 Tools and methods for IP (TOOLIP) project is developing such an approach to reusable IP cores, with system level modelling and verification techniques, and a seamless design flow that accepts existing and emerging tools. TOOLIP's overall objective is to provide a fully documented design flow with recommendations and guidelines based on IP reuse and exchange. The result should be decreased time to market for large-scale devices with high system reliability and reduced overall cost. The best practices proposed in TOOLIP will enable European industry to secure and safeguard leadership in key markets such as Internet, digital consumer electronics and wireless communications.

MESDIE (A509)

Back-end physical design is equally important for faster, more cost-effective and more highly integrated devices. However, as circuits grow in complexity, operate faster and reduce in size, the issues of electromagnetic compatibility and parasitic emissions become ever more significant. The MEDEA+ A509 Microelectronic EMC system design for high-density interconnect and high-frequency environment (MESDIE) project is developing a coherent approach to overcoming these problems at both chip and high-density packaging levels using circuit models and simulation techniques for parasitic behaviour simulation for the benefit of the European microelectronics industry.

The same area is being tackled in the MEDEA+ T102 Application specific design for ESD and substrate effects project. ASDESE is developing methodologies to simulate the influence of electrostatic discharge (ESD) and feedback through substrate coupling so designers can apply necessary changes or protective measures before manufacture. First-time-right is essential to reduce time to market, so chip producers cannot afford to detect malfunctions only after testing of processed wafers and then to start redesigning.

ASDESE is evaluating new test structures and circuits using a variety of computer simulation techniques. While software exists for modelling substrate coupling, it is not proven for productive designs. Therefore, the project is developing new software and integrating it into the conventional design flow process to make it more effective. An important goal is to define a common interface for substrate simulation tools within a widely used design environment, making it possible to choose a tool that fits the problem.

ASSOCIATE (A503)

Finally, the A503 Advanced solutions for SoC innovative testing in Europe (ASSOCIATE) project is meeting the new challenges in the debugging and testing of SoC devices based on the creation and application of reusable, interoperable IP blocks. The objective is to streamline debugging and testing throughout the product life cycle, and to provide cost-effective methods appropriate to high-volume production - securing the competitiveness of key European industry sectors.

ASSOCIATE has links with a MEDEA+ technology project T101 Technology-driven design and test for system innovation on silicon (TechnoDat). As ASSOCIATE focuses on generic solutions in design for test, design for debug and test application, a high level of synergy exists between these three projects.

The emerging tools will be able to handle very large and heterogeneous circuits with a high degree of accuracy down to the sub-micron and sub-nanosecond level. This is not only so as to produce dense designs, but also to provide for the efficient means of debugging and testing that are crucial to the future of the European microelectronics industry.