ARTICLE OCTOBER 2003

EDA ROADMAP SHOWS WAY AHEAD FOR SOCS

Increased investment and higher productivity in electronic design automation (EDA) are essential, especially to build on European strengths in application-specific integrated circuits (ASICs), to handle the move to sub-90nm chip designs and, most importantly, to make the most of the increasing integration of microelectronics into complete system-on-chip (SoC) devices. The fourth edition of the MEDEA+ EDA roadmap, released in June 2003, focuses strongly on an in-depth analysis of the European solutions required to drive progress for early access to silicon SoC products.

In the past, improvements in silicon SoC capabilities have been obtained through evolution in the silicon process itself. However, application of advanced EDA solutions is now becoming critical to ensure early availability of new products in the latest silicon technologies ? an area where Europe has been lagging behind the USA.

Top-down design flow

It is now vital to develop a global European strategy to engineer design solutions more rapidly, in a top-down design flow, with a choice of silicon application platforms, and to develop system intellectual property (IP) for reuse in the next generation of products. Such reusable IP should include basic digital functions and value-added properties such as analogue and radio-frequency functions (areas where Europe excels), embedded SRAM, DRAM and non-volatile memories. Educating new generations of multidisciplinary designers to understand physics, hardware and software, is essential to achieve these aims.

The MEDEA+ EDA roadmap is intended to provide an efficient knowledge-management tool that assembles all the key players ? academic, research centres and microelectronics systems houses. It is also directed at improving European competitiveness by reducing time to market.

A major change in the past decade has been the move from application-specific integrated circuits (ASICs) aimed at all markets to differentiated ICs dedicated to specific customers. These new devices have more computational power and greater storage capabilities and often need analogue interfaces to interface with the real world. There will also be an increasing role for hardware-dependent software ? often requiring more development resources than the hardware itself.

Use of application platforms for mobile telephony, multimedia terminals, automotive electronics and general fixed and wireless communications has made it possible to improve design efficiency by exploiting application-driven design flows, reusing component libraries and building blocks, and better overall production optimisation. It is forecast that by 2005, some 70% of the market for differentiated products will be in SoCs ? accounting for 30% of the overall semiconductor market. But, while the SoC market will be huge, it will be highly competitive ? and EDA will inevitably become the key differentiator for fast market response.

Dramatic increase in IP reuse

The main changes in electronic design over the coming decade will be a dramatic increase in IP reuse ? up to 96% of the area of a chip ? based on standardisation and reusability of design blocks, with memory use as much as 70% of chip area. And power consumption will become a critical parameter. In 2000, the 0.18-micron technology node offered 5.106 K-gates/cm2 with 1000 million instructions per second per Watt (MIPS/W) but, by 2004, 90nm technology should provide 30.106 K-gates/cm2 with 2200 MIPS/W and, by 2011, 50nm technology should ensure 200.106 K-gates/cm2 with 4000 MIPS/W.

According to the MEDEA+ EDA roadmap, release 2003, SoC designs in 2011 will include 100 million gates or several hundred million memory cells. Major problems will lie in managing the complexity of the hardware and software, ensuring that detailed implementations work, handling on-chip communications and still reducing time to market. The answer lies in top-down design with more formal definition of SoC specifications, and increased design efficiency and optimisation through the use of higher levels of abstraction ? requiring standardisation of design languages. Standardisation is crucial at all steps in the design flow ? with appropriate design tools offering the same semantics and syntax whoever supplies them, and the availability of easily reusable IP.

Design integrity bottlenecks that will still have to be overcome include accurate simulation of interconnects, electromagnetic compatibility and interference, and transient faults caused by radiation effects. This will require fault-tolerant or dynamically reconfigurable implementations.

SoC devices effectively involve combining the equivalent of several ASIC boards on a single chip. This will therefore require a new approach to design involving architectural constraints, hardware and software. No single designer or location will be able to handle the huge design task. It will require distributed design teams possessing multidisciplinary skills, using new forms of work organisation and operating in a common user-friendly design environment.

Tighter production control

System sign-off will play an important role in controlling manufacturing costs and speeding time to market by ensuring prototypes are good at the first silicon processing. This will increasingly involve the final user in the formalisation of the specification to provide agreement on the way the final product will look and feel. It depends on the study of usages and will often be based on user validation of a virtual representation of the final object before it is realised.

Design for manufacturability is also developing as a new domain linking technology and design. With new SoCs relying on sub-100nm processes, manufacturing yield will depend on the detailed performance of every single piece of processing equipment. This will make compulsory a detailed optimisation of every process step against design rules as yield becomes strongly feature- rather than area-based, as at present. The result, however, should be huge savings in production ramp-up with more good dies per wafer.

Overall, the European microelectronics industry ? chipmakers and systems houses as well as universities and research laboratories ? must continue its already strong involvement in the MEDEA+ EDA roadmap initiative to ensure a permanent level of dialogue and exchange to strengthen the European EDA community. This will facilitate the adoption of standards and the development of easier to use solutions to EDA overall.