The overall objective of this project is to provide within 3 years an industrial source of large diameter strained SOI. The project aims at building a strained SOI technological platform gathering the main European actors in substrates, metrology and ICs in order to fasten the development of high mobility (strained) SOI wafers and to shorten their introduction in a IC fab environment. The substrate platform encompasses the processing compatibility of these new substrates with sub 65nm technology in the industrial environment of ICs makers. High mobility "strained Si" and "SOI" are two breakthroughs that the consortium wish to combine in one single technology platform for high performance ICs.

Goal of the project is to shorten the learning curve of the latest generation CMOS technology from 18 to 12 months (faster) after 'first silicon out' yielding at least 75% yield. Key is to reduce fab-wide cycle time from 2 to 1.0 days per mask layer for standard lots and from 0.75 to 0.35 for fast prototyping hot lots and to attain an additional 5% defect reduction and yield increase in the mature production/high volume stage.

The goal of the project is the development of advanced process modules and transistor architectures and demonstration of a full CMOS 45nm process technology in European 300 mm manufacturing industrial facilities. For the first time in the development of successive CMOS generations, within the context of JESSI/MEDEA/MEDEA+ projects, the present proposal targets both CMOS logic and DRAM process technologies and promotes a synergy between the competences of the major European IC manufacturers poles, on the one hand in Crolles the ALLIANCE (STMicroelectronics, PHILIPS Semiconductors, FREESCALE) and on the other hand in Dresden: INFINEON

The objectives of this project are to integrate performance boosters in Fully and Partially Depleted SOI technologies for Low Power and High Performance, to validate their impact by fabricating complex 45nm node demonstrators directly comparable with bulk Si and to develop design kits and SOI-adapted circuit design for the evaluation by application designers. The consortium is composed by two substrate suppliers and two academic laboratories for the development/production of advanced substrates, two IDM and a research institute to integrate the technology and fabricate the test circuits and, with the support of a design house, produce the design kits.

Goal of the project is to create fully integrated technology platforms for the embedding of NVM functions in sub-100nm CMOS technologies (process, demonstrator, test and reliability infrastructure), with the purpose to support the increasing need for on-chip re-programmability and configurability. It is further aimed at to improve competitiveness by reducing the time required to validate and industrialize new NVM cell concepts and process options.

The goal of the project is the development of new accelerated test and simulation based methodologies for verification and prediction of lifetime under changing conditions. Resulting methodologies, if generally accepted, will be standardised. Lifetime predictions for changing conditions will be possible and higher quality of electronic systems will be achieved. The project consortium ensures the spread and acceptance of that new, common methodology within the industry.

The project is the development and comparison of new generations of Smart Power Technologies. Several technology approaches will be explored and developed: deep sub-micron BCD-MOS and innovative SOI substrate material. It will therefore allow comparison of performances of several technologies.

The project aims at the establishment of silicon technology platforms for emerging high frequency and mm-wave consumer applications like 77GHz automotive radars, 60GHz wireless networking (WLAN and WPAN) and 100Gbit/s optical data communications.A consortium of 10 partners from 3 countries will work together.

Goal of the project is to develop new materials for memories and capacitors, which will be needed to fulfil future technology requirements. Concerning capacitors the main goal is to increase the capacitance per surface area, with very low leakage currents and excellent RF linearity to enable integration of currently discrete components into the chip. In the memory field DRAM structures and additionally new PCRAM materials to be deposited by means of (PE)ALD techniques will be evaluated.

The goal of the project is to develop the technology for a European EUV lithographic platform for volume manufacturing. In this context a platform is the basic lithographic system, which is expected to serve the industry for the next decade. The results will enable the semiconductor industry to produce in 2009 in accordance to the ITRS roadmap, ICs for the 32nm node. Critical key sub-systems of the lithographic tool will be integrated at the end of the project in order to demonstrate the feasibility of the system and the technology target specifications.

Goal of the project is to develop means to control mask costs and to safeguard the European autonomy in masks for nano-electronics. It will combine broad common efforts from IC designers, mask makers, material providers, software houses and mask users in order to create a leading edge supply chain for very high advanced masks in a zero defect quality concept for final product.

Goals of the project are the development of lithographic equipment making use of immersion technology, reticle technology, low k1 enhancement technology and resist processes to support the IC industry with production worthy lithographic solutions for the 55 to 45 nm node and beyond. This project will enhance the possibility for European lithography related industry to maintain and improve their world wide competitive position.

Goals of the project are to establish and assess a Step and repeat UV-based NanoImprint Lithography (UV-NIL) "virtual" infrastructure for the CMOS 32 nm node requirements.
To realise this ambitious aim the project will create a running "virtual" infrastructure including all aspects, such as imprint tool development, template fabrication including metrology repair processes as well as process development and the metrology up to the application in a consolidated action. With this infrastructure, the FANTASTIC project will close the gaps and generate convincing data by precise and comprehensive analysis and a complete assessment for integration of this technology into the 32nm CMOS node fabrication.

Project goals are to decrease cycle time excursions and to simplify mask qualification procedures for the 193nm lithography supply chain.

The overall objective of HI-MISSION is to develop an innovative technology and design platform for RF Microsystems applications. The platform will enable flexible microwave design, decreasing substantially new product development time and facilitating new concept verification.
The main goal will be to develop a technology platform for RF SiP/SoC Applications in the field of automotive, military radar and microwave communication systems.

The objective of this project is to provide the enabling basic design environment, required for the creation of a wide variety of compact systems. The consortium aims at shorter time to market, less redesign cycles, and more reliable design and products. The three EU semiconductor companies NXP, Infineon, and STMicroelectronics together with Bosch, three SMEs and four R & D institutes from 5 EU countries will work together to combine their knowledge and expertise for the creation of a SiP Chip/Package/Board Co-design platform with focus on European applications.