The MIMOWA project aims at simulating, implementing, validating and evaluating wireless MIMO (Multiple In Multiple Out) building blocks, i.e. IP, Silicon and FPGA content for different air interfaces. Focus will be on Cellular 3G (Long Term evolution), WiMAX (Fixed and mobile), and WiFi. The MIMO blocks are intended to enable the wireless semiconductor industry together with the infrastructure and the test and measurement industry to fasten the standardisation and the roll out of new wireless MIMO enabled schemes.
Furthermore a longer term investigation will enable the potential sharing of MIMO building blocks across standards, fostering the integration/convergence and the re-use of development for the different standards.

SR2 project focuses on novel and ultra low power radio components in the Wireless Personal and Body Area Network landscapes. Its ultimate goals are to develop multi-standard System-on-Chips, assess their coexistence performance and integrate them in selected applications for home monitoring and automation.

Design and implementation strategy for low cost, ultra-high data rate streaming applications in the 60GHz band (kiosk-downloading), Hardware demonstrators, standardisation in mm-wave domain Multimedia as key driver for S/C business.

This project aims at boosting the European semiconductor, consumer electronics and content distribution industry in order to become leading in the high definition media distribution and storage market through advanced co development. This will be based on an innovative storage standard called BLU RAY currently under development.

UPPERMOST will provide for the enabling platform for ubiquitous communications. UPPERMOST will research, develop and demonstrate cost-effective, low-power, highly adaptive and reconfigurable technical solutions for future mobile terminals, by conducting studies at system,sub-system (i.e. radio architecture) and component levels.

The goal of the project SWANS is to define a generic silicon platform aiming at integrating analogue and digital IP blocks for future wireless sensor nodes. This platform will be used to demonstrate functional IP blocks, macrocells and chipsets for 5 application classes: aeronautic, health/fitness, homeland security, automotive and environmental monitoring. The project will allow the European industry to face the future needs of European consumers for low cost autonomous devices bringing more security and more services to their daily environment: transportation (automotive, aeronautics), home (medical, environmental), public spaces (fitness, homeland security).

High-end CCD imagers and video processing for applications in the professional broadcast, machine vision, medical, digital photography and other markets. The focus of the project will be on a flexible video processing architecture, prototype ICs and systems including interconnect and networking architectures. Results will include high resolution CCD imager prototypes up to 4 times faster than today, a new video processing ASIC for the imager, enhanced IPs and methodologies thereof.

The project brings together technology suppliers for the imaging chain in the broadcast (consumer entertainment) and industrial markets. Both the image capture and play-out (storage, Set Top Box and connectivity to displays) are represented to short-circuit both ends of the chain and to secure that standards set do not pose problems at the other end of the chain. It builds the bricks required to initiate the next television revolution: the 3D TV. This involves in particular, the “beyond HD” camera acquisition, the holographic storage and the 3D enable connectivity. In the medium term it creates technologies in Europe that can effectively sustain and develop the interests of European companies and media, by establishing innovative flagships products and business model in the first steps beyond HDTV and in 2D+Z image capture solutions. These technology clusters can then interact to form the basis for commercial R&D and create a European role in the core technologies for immersive imaging like 3DTV for consumer and high data rate professional applications.

The project's primary goal is to develop complete HW and embedded SW platforms, that will enable the European Community (Industrial or Government Operators, Terminals and Smart-cards companies, Silicon vendors) to take full profit of the enormous potentialities offered by the development of fixed or mobile e-Services such as EU Citizen Card and Mobile Multimedia.

Advanced (microelectronics and embedded SW) secure platforms for all needed e-administrative applications requested at European level. e-identity cards based on ECC Match- on-Card Biometric capabilities.

This project aims at developing a European automotive reference platform for assistance systems to increase road safety. The project based on optical recognition and image processing technologies will be developed in order to sustain the stringent automotive environment and also to meet the design-to-cost-effectiveness for high volume car application.

This project will focus on developing the chipsets and middleware required for building these networks and new sensors will be developed that will measure environmental factors and driver data.  Using this data to monitor driver’s vital signs, and adapting the in-car environment accordingly will increase the driver wellness.  By doing so the likelihood of accidents will decrease.  Furthermore, this data can be used for detecting health care problems, increasing the efficiency of health care processionals and reducing the environmental impact of a vehicle.  Developments will include Sensors (e.g. a wellness sensor), Application specific flexible processors, Communications modules (wired and wireless), Supporting chipsets.

General project goals:
R&D of a family of HW/embedded SW silicon components enforcing secure and trusted computing for the areas of Consumer, Computer, Telecommunications and Wireless.
Development of a trust concept and architecture elements usable in other European industrial segments such as automotive, industrial, aeronautics (especially in their content acquisition and payment, ticketing and DRM aspects)
Relevant European contributions related to Trusted Computing standards while keeping inter-operability with existing US-led or Asian initiatives. 

The project will deliver:
- Requirements- Impact report on TSC implications on infrastructure
- Protection Profiles for computer and mobile environment
- Management procedures for computer and mobile TPM available: code and documentation
- Two sets of Trusted components on Silicon (HW+ Embedded SW)
- Feasibility Mock-ups for all application domains including evaluations

This project addresses the increasing problem of interference that together with the parasitic effects of new IC processes are affecting the reliability of modern electronic systems. Nanometer circuits, micro-electronics, micro-system technology and power electronic systems are already part of our daily life. However, these systems encounter many problems with natural and artificial interferences coming from various sources i.e. those circuits are becoming sources of interference (to) themselves. The project aims at improving the Reliability of Applications based on these Electronic Systems.

NanoTEST will create breakthroughs in manufacturing test, in the area of costs as well as achieved quality and time to market. Both future SoC technology nodes and future SiP packages are addressed. Accompanied by flows, tools and standards, the project results will be ready for exploitation on time to support emerging technologies. The test technology resulting from NanoTEST will support new business development in the domains of telecom, computing, and automotive and industrial electronics, mainly driven by reduced test costs for new packages, SoCs with embedded RF and mixed-signal, and MEMS products.

With circuit size potentially reaching one billion transistors by end 2008, traditional bus-based single-clock architectures become unusable for commercial circuits. Starting from successful design approaches (e.g. Multi-Processors, Asynchronous Design) proven during MEDEA+ phase-1, NEVA intends to raise 3 main innovations up to industrial level: communication-centric design for fast simulation and execution, infrastructures for real-time applications, and a complete design flow to implement asynchronous techniques. Datastream applications, mainly from the Video field, will be used as drivers, with a target computing power of 1 GOPS per chip.1. The project focuses on Networks on Chips with video computing as main driving application. The goal is to allow designers and application engineers to cope with emerging applications resulting from Multimedia/Communication convergence.

While applications require smaller voltages and higher frequencies, miniaturisation adds new risks of voltage distortions. To reduce design iterations and avoid unreliability or failures, ROBIN aims at preventing these effects very soon in the design flow. The project will address signal corruption in Systems-in-Package either at macro-level (power distribution,substrate) or micro-level (interconnect crosstalks, natural radiations). By considering manufacturing constraints, optimal trade-offs will be defined between circuit robustness and efficient use of technology, down to 45 nm.

The LoMoSA+ project aims at the creation of a low-power expertise for mobile and multimedia applications by initiating the development of a European low-power System-on-Chip (SoC) platform, consisting of an interacting combination of (architectural) models, design flows and methodologies, hardware design components, embedded software and test-benches.

The project targets yield improvements through innovative design techniques in terms of redundancy, high yield libraries, yield oriented design-optimisation and place-and-route tools, and post-layout optimisations. These solutions will offer yield loss prevention and recovery throughout the whole design flow. Design for Reliability is forming a natural complement to Design for Yield and this project offers the opportunity to follow the same approach (statistical in nature) for both. The 3 main European Silicon Manufacturers and 4 CAD Companies supported by 2 labs team up in HONEY to propose new generic solutions. Implementations will mainly address 65 and 45 nm, with a retrofit to 90 nm and experiments on 32 nm.

Hardware dependant Software (HdS) solutions to improve IP integration in the SoC design process (quality / productivity): To separate the Operating System (OS) and the application software from the underlying hardware and HdS for efficiency, dependability, flexibility and manageability. Systematic, highly automated HW/SW-integration of IP.

Improve the design refinement process of Embedded Analog Mixed-Signal heterog. SoC and SiP: Reduce "design time & cost" Digital HW/SW system RF circuits, sensors, network protocol.

Press release

Project website

Design and application of multi-core processor architectures targeting tera-flops performance. Topics are In-Network Cache Coherence Protocol on NoC-based architecture, Scalable Tera Bit/s IO design, Applic. Specific GALS NoC design, optimal Compilation for Multi-Core/Multi-Thread Processor.